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MX9691A 1 p/n:pm0539 rev. 1.0, oct. 02, 1998 single chip solid state disk controller features host interface ? fully compatible with pcmcia release 2.1, and pc card ata release 1.02 specification. ? compatible with all pc card services and socket service. ? fast ata host-to-buffer burst transfer rates up to 20mb/ sec. which support pio mode 4(16.6mb/sec) and dma mode 3(16.6mb/sec). ? automatic sensing of pcmcia or ata host interface. ? integrated pcmcia attribute memory of 256 bytes (cis). - cis and buffer ram use same sram area to simplify internal bus design ? pcmcia card configuration register support. ? polarity control for host reset signal. ? pcmcia twin card support. ? pcmcia based ata address decode support. ? emulate the ibm task file for pc/at. ? separate status for bus reset and host program reset. ? separate host and disk interrupt pins. flash memory interface ? support all the control signals to execute read/write/ erase operation for flash memory. ? upto 32mb(unformatted) capacity for 16 pcs. 16mbit flash memory or 64mb(unformatted) capacity for 16 pcs. 32mbit flash memory. ? flash memory power down or write protect control support. - don't power down the flash memory chip which used to store firmware ? flash memory ready/busy status detect. ? inverted data bus control to reduce program operation in dos fat and ecc code field. ? optional store firmware in flash memory array w/o externalrom. - shadow rom control to allow code fetch during data program or erase ? media speed is upto 8mb/sec, sustain read data rate and 125kb/sec write data rate. buffer ram control ? dual port circular buffer ram control ? 1kb data buffer ram. ? automatically correct error data in buffer ram. - single word error correct and double word detect. ? provide logic to speed up buffer ram access. ? support 8 bit as well as 16 bit transfer on host bus. dsp core ? high performance mx93011 dsp (21mips) core. ? 4kb internal ram(direct access). ? 2kb internal expansion ram(indirect access) for store data or shadow rom space. ? ice debugging mode supported to ease system verification. ? lower power and automatic power saving operation technology ? 128 pin lqfp ? 0.6um low-power, high-speed cmos technology. ?5v 10% or 3.3v 5% utility support ? upload firmware from host. ? physical devices test. ? preformat. ? cis manufacturer code and model code edit.
2 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 pin configuration 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ha2 reg# ha1 spkr ha0 gnd stschg hd0 hd8 hd1 hd9 hd2 hd10 iois16# pwr_rst test vcc x1 x2 gnd romwr# romcs# xf# hlda# vcc x32i x32o gnd dce# pce# wr# rd# fa16 fa15 a14 a13 a12 led# gnd a11 a10 a9 a8 fa19 fry/fby# int1# nmi# hold# vcc wrflash0# wrflash1# fa18 fa17 a15 a7 a6 gnd a5 a4 a3 a2 a1 a0 pwd0# d7 d6 d5 d4 d3 gnd d2 d1 d0 rdflash0# fce7# fce2# vcc fce1# fce0# gnd fce6# fce5# fce4# fce3# vcc rdflash1# d8 d9 d10 d11 gnd d12 d13 d14 d15 pwd1# hd3 hd11 hd4 hd12 hd5 hd13 hd6 hd14 gnd ireq# inpack# hd7 hd15 hce1# hce2# ha10 vcc hoe# ior# ha9 gnd iow# ha8 vcc hwe# ha7 ha6 ha5 hreset ha4 wait ha3 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MX9691A
3 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 general description the macronix's solid state disk controller is fully inte- grated flash memory controller that provides all the con- trol logic for a pc card ata flash memory. the MX9691A combines 1kb dual-port buffer and buffer manager, inte- grated mx93011 dsp core , and a complete host inter- face for both the pc card ata and ata standard. the MX9691A is typically configured with up to 32mb(unformatted) capacity for 16 pcs. 16mbit flash memory or 64mb(unformatted) capacity for 16 pcs. 32mbit flash memory. the MX9691A supports all the control signals to execute read/write/erase operation for flash memory chip. the MX9691A is fully compliant with the pc card ata specification. it includes 256 bytes of integrated attribute memory(for the required card information structure) and four card configuration registers. the pcmcia device driver can access the MX9691A ata command block through four different modes by writing the different modes by writing the configuration index of the attribute memory configuration option register. pin description host interface symbol no. type description ha[10:0] 92,94, 96-97, i host address line 10-0. 99,101-103, these pins include internal pull-up resistors. 106,109,113 hd[15:0] 84-89,116-117, i/o host data line 15-0. 121-128 these pins include internal bus holder circuit that keep previous state when tri-state. hoe#,hwe# 104,111 i host memory read/write/mode select : both pins include internal pull- up resistors that is default in pcmcia mode. ior#,iow# 107,110 i host i/o access. both pins include internal pull-up resistors. hreset/ 100 i the host reset signal, when active, initializes the control/status hreset# registers and stops any command in process.in pcmcia mode, the signal is active high. in ata extension mode, this signal is active low. this signal include internal pull-down resistor. wait/ 98 o,od wait or input channel ready : in both pcmcia and ata iochrdy extension modes, this signal holds host transfers until the controller is ready to respond. rdy/bsy#/ 119 o,z ready/busy or host interrupt : in pcmcia mode, this signal ireq#/ has two functions. in pcmcia common memory mode, this signal is hostint ready/busy. it is asserted busy by the reset logic, and can be deasserted by the local uc. in pcmcia i/o mode, this signal is ireq#. in ata extension mode, this active high signal is hostint, which, when enable, send an interrupt to the host.
4 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 symbol no. type description wp/iocs16# 83 o,od write protect or 16-bit i/o transfer : in pcmcia mode, this bit has two functions. in pcmcia common-memory mode,this signal indicates write protect. in pcmcia i/o mode, when iois16# is as serted low, it indicates that a 16-bit data transfer is active on pcmcia bus. in ata extension mode, the iocs16# signal indicates that a 16-bit buffer transfer is active on the host bus. this open drain signal is only driven on assertion(low). reg#/dack# 95 i attribute memory and i/o select : in pcmcia mode, this signal is used to select attribute memory and i/o space. in ata extension mode, this signal is used during dma with the dreq, ior# and iow# signals to transfer data between the host and the MX9691A. this pin includes an internal pull-up resistor. hce1#/ 115 i card enable 1 or chip select 0: in pcmcia mode,this signal is card cs1fx# enable 1. this signal can enable either even or odd numbered-address bytes onto hd7:0. in ata extension mode, this signal accesses the MX9691A command block registers. this input is ignored during dma data transfer, i.e. when the dack# signal is low. this pin includes an internal pull-up resistor. hce2#/ 114 i card enable 2 or chip select 1: in pcmcia mode,this signal is card cs3fx# enable 2. this signal can enable odd numbered-address bytes onto hd15:8. in ata extension mode, this signal accesses the MX9691A control block registers. this pin includes an internal pull-up resistor. inpack#/ 118 o input acknowledge or dma request : in pcmcia mode, this signal is dreq asserted when the MX9691A is configured to respond to i/o card read cycles at all addresses. in ata extension mode, this signal is dreq and is issued during dma transfers to indicate that the MX9691A is ready for dma transfer. spkr/dasp# 93 i/o speaker or slave present : in pcmcia mode, the output-enable for this signal is controlled by the card configuration registers. in ata extension mode, this signal is used as the slave-present detector. stschg/ 90 i/o status change or pass diagnostics : in pcmcia mode, this signal is pdiag# used to indicate changes in the rdy/bsy#,wp signals in card con figuration registers. in ata extension mode, this active low signal is used between two embedded ata drive to indicate that the drive in slave mode has passed diagnostics.
5 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 microcontroller interface : symbol no. type description d[15:0] 33-37, i/o dsp io/ram/rom/flash memory array external data bus. these 39-41, pins in clude internal pull-up resistors. 55-58, 60-63 a[15:0] 3-5, i/o in normal mode, these signals are output that used as dsp io/ram/ 8-11, rom external address. a14-a0 are for flash memory array address 22-24, also. in upgrade mode, these address is used for rom address that 26-31 controlled by cyh,cyl registers. in ice debugging mode, these ad dress are input,asserted by external mx93011 dsp. the internal dsp is disabled. these pins include internal pull-up resistors. pce# 67 i/o in normal mode, this signal is output that is used as external program chip enable. in upgrade mode, this signal is drived to high. in ice de bugging mode, this signal is input, asserted by external mx93011 dsp. the internal dsp is disabled. this pin includes a bus holder circuit. dce# 68 i/o in normal mode, this signal is output that is used as external data chip enable. in upgrade mode, this signal is drived to high. in ice debug ging mode, this signal is input, asserted by external mx93011 dsp. the internal dsp is disabled. this pin includes a bus holder circuit. rd# 65 i/o in normal mode, this signal is output that is used as dsp io/ram/ rom external read. in upgrade mode, this signal is output and as serted when the data register is read in host interface. in ice debug ging mode, this signal is input, asserted by external mx93011 dsp. the internal dsp is disabled. this pin includes a bus holder circuit. wr# 66 i/o in normal mode, this signal is output that is used as dsp io/ram/ rom external write. in upgrade mode, this signal is drived to high. in ice debugging mode, this signal is input, asserted by external mx93011 dsp. the internal dsp is disabled. this pin includes a bus holder cir cuit. nmi# 15 i non maskable interrupt pin. this pin includes an pull-up resistor. int1# 14 i/o in normal mode, this signal is input that is used as interrupt pin. interrupt will be internally asserted also when data transfer done, or command end. in ice debugging mode, this signal is output and as serted when data transfer done, or command end. this pin includes an pull-up resistor.
6 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 symbol no. type description hold# 16 i/o in normal mode, this signal is input that is used as holding dsp clock down and release bus. bus hold will be internally asserted also when upgrade mode enable. in ice debugging mode, this signal is output and asserted when upgrade mode enable. in ice debugging mode, this signal is output and asserted when upgrade mode enable. this pin includes an pull-up resistor. hlda# 73 i/o in normal mode, this signal is output that is used as ack to hold# signal. this signal will be internally sent to pcmcia/ata interface also when upgrade mode enable. in ice debugging mode, this signal is input and ack to hold# when upgrade mode enable. this pin in cludes an pull-up resistor. xf#/cpurst# 74 o external flag, this pin can be directly written by one dsp instruction. default inactive (logic high). in ice debugging mode, this signal is used to reset cpu. flash memory interface : symbol no. type description fa19/cle 12 o in random mode, this signal is used as flash memory chip high address line 19. in sequential mode, this signal is used as flash memory chip command latch enable. fa18/ale/ 20 i/o in random mode, this signal is used as flash memory chip high address line 18. in sequential mode, this signal is used as flash memory chip address latch enable. this signal is used to select whether the MX9691A initializes in normal mode or in ice debugging mode at power- on reset. if this pin go high, then the MX9691A will switch to normal mode at power-on reset,and if this pin remains low, then the mx9691 a will initializes in ice debugging mode. this pin includes an internal pull-up resistor. icemode ice debugging mode select : icemode=1 > nor mal mode icemode=0 > ice deb ugging mode
7 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 symbol no. type description fa17/erom 21 i/o this signal is used as flash memory chip high address line 17. this signal is used to select whether the firmware store in flash memory array or in separate external rom at power-on reset. if this pin go high, then the firmware will be executed in flash memory array, and if this pin remains low, then the firmware will be executed in separate external rom. store firmware in external rom or flash memory array: erom = 0 > store in exter nal rom erom = 1 > store in flash memory array this pin includes an internal pull-up resistor. fa[16:15]/ 1-2 i/o this signal is used as flash memory chip high address line 16-15. these atadet[1:0] signals are used to select configuration in ata extension mode at power- on reset. atadet1 is connected to dsp's ipt1. atadet0 is connected to dsp's ipt0. vdd is connected to ipt2. master/slave selection in ata mode : atadet1 atadet0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives this power-on configuration can be accessed from pcmcia/ata port 601ch bit3-2. these pins include internal pull-up resistors. rdflash1# 54 o flash memory ouptut enable 1 for bank1: this signal will be asserted by flash memory read operation when flash memory read address latch, port 601dh bit 8 = 1(i.e. fa23=1). note: flash memory access window is mapped to 32kw data and code space 8000h~ffffh. rdflash0# 42 o flash memory ouptut enable 0 for bank0: this signal will be asserted by flash memory read operation when flash memory read address latch, port 601dh bit 8 = 0(i.e. fa23=0). wrflash1# 19 o flash memory write enable 1 for bank1: this signal will be asserted by flash memory write operation when flash memory write address latch, port 601fh bit 8 = 1(i.e. fa23=1). wrflash0# 18 o flash memory write enable 0 for bank0: this signal will be asserted by flash memory write operation when flash memory write address latch, port 601fh bit 8 = 0(i.e. fa23=0).
8 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 symbol no. type description fce[7:0]# 43-44,46-47, o flash memory chip enable 7-0 : 49-52 in random mode, these signals are decoded from port 601dh bit 7-5 when flash memory read or port 601fh bit 7-5 when flash memory write. decoding combination : bit7 bit6 bit5 fce[7:0]# 0 0 0 11111110 0 0 1 11111011 0 1 0 11101111 0 1 1 10111111 1 0 0 11111101 1 0 1 11110111 1 1 0 11011111 1 1 1 01111111 in sequential mode, these are decoded from port 601dh bit 7-5 only when port 601eh bit 2 is set. pwd0# 32 o deep power down output 0 for bank0: this signal will put the flash memory chips of bank0 in deep power-down mode. pwd0# is active low;pwd0# high enables normal operation. pwd0# also locks out erase or program operation when active low providing data protection during power transitions. power down pin pwd0# will be active if fa23=1. pwd1# 64 o deep power down output 1 for bank1: this signal will put the flash memory chips of bank1 in deep power-down mode. pwd1# is active low;pwd1# high enables normal operation. pwd1# also locks out erase or program operation when active low providing data protection during power transitions. power down pin pwd1# will be active if fa23=0. fry/fby# 13 i flash memory ready/busy input: this signal indicate the state of erase or program operation in flash memory chips.this pin includes an internal pull-up resistor.
9 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 control rom interface : symbol no. type description romcs#/ 75 o rom chip select/flash memory data buffer enable : in normal mode, fwin# this signal is used as rom chip enable if firmware that stored in external rom. in ice debugging mode, this signal is used as flash memory data buffer (74640) enable if firmware that stored in flash memory array. romwr#/ 76 o rom write enable/flash memory data buffer direction control: in fdir normal mode, this signal is used as rom write enable if firmware that stored in external rom. in ice debugging mode, this signal is used as flash memory data buffer (74640) direction control if firmware that stored in flash memory array. miscellaneous : symbol no. type description x1 79 i crystal input. x2 78 o crystal ouput. x32i 71 i 32k crystal input. x32o 70 i 32k crystal output. test 81 i this signal is used to select the main system clock, either from external clock source if this signal is high or from internal pll circuit if this signal is low. this pin includes an internal pull-up resistor. pwr_rst# 82 i power on reset, cmos schmite-triggered: the MX9691A include debouncing circuit to stabilize internal dsp reset signal. led# 6 o led output: this signal is connected to external led in debugging system to indicate system status. the led will be turn-on during reset. the contorl firmware will turn off the led after h/w initialization and pass diagnostics. if system fail, the control firmware will flash the led to indicate some error occur. this signal will be high if port 601ch bit0 set to 1 or optr bit2 set to 1. vcc 17,45,53,72, 5 volt or 3.3 volt power pin 80,105,112 gnd 7,25,38,48, ground pin 59,69,77,91, 108,120
10 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 mx93011 dsp core clock & reset register bank 1kb buffer ram 4kb internal ram 2kb internal ram flash memory control ecc control logic 256 byte cis ram MX9691A signal chip solid state disk controller buffer ram control external memory bus clock host interface pcmcia/ata flash interface pcmcia/ata interface functional and operation description block diagram
11 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 power-on detection: (1). store firmware in external rom or flash memory array : fa17/erom = 0 > store in exter nal rom fa17/erom = 1 > store in flash memory array (2). master/slave selection in ata extension mode : fa16/atadet1 fa15/atadet0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives (3). ice debugging mode select : fa18/icemdoe = 0 > ice deb ugging mode fa18/icemode = 1 > nor mal mode (4). flash memory data buffer control romcs# is replaced by fwin# if ice debugging mode & firmware in flash memory array romwr# is replaced by fdir if ice debugging mode&firmware in flash memory array (5). pcmcia or ata extension select hoe# hwe# mode 0 0 ata extension mode others pcmcia mode system memory map : (1). data space : address function & usage 0000h~007fh internal ram (128w) to store control variables 0080h~07ffh internal ram(1920w) for flash memory algorithm usage 0800h~5fffh user define (22kw) 6000h~63ffh i/o range(1kw): ata ctl. use i/o range (6000h~601fh) 6400h~6fffh user define (3kw) 7000h~73ffh user define (1kw) 7400h~77ffh internal ram (1kw) for expansion ram or shadow rom space 7800h~7fffh rom data space(2kw) 8000h~ffffh flash memory access windows(32kw) (2). program space : address function & usage 0000h~77ffh rom program space (32kw) 7800h~7fffh unused 8000h~ffffh flash memory access windows(32kw)
12 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 registers definition: (1). register list : type of register location pcmcia/ata interface 6000h, 6001h, 6002h, 6003h, 6004h, 6005h, 6006h, 6007h, 600bh, 6010h, 6011h, 6012h, 6013h, 6019h, 601ah, 601bh, 601ch pc interrupt control 6009h, 600ah buffer manager and dma 6008h, 6014h, 6015h, 6016h, 6017h, 6018h ecc control 600ch, 600dh, 600eh, 600fh flash memory interface 601dh, 601eh, 601fh (2). register description : port 6000h : bit function description at control/status register default reset value : 01h 7 r/w: drive ready (drive 0) 6 r/w: drive seek complete (drive 0) 5 r/w: corrected data 4 r: ata int. enable 3 r: at software reset 2 r/w: host interrupt 1 r/w: error bit 0 r/w: busy bit port 6001h : bit function description default reset value : 00h 7:0 r/w: error register (map to command block 1f1h) port 6002h : bit function description default reset value : 01h 7:0 r/w: sector count register (map to command block 1f2h)
13 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 port 6003h : bit function description default reset value : 01h 7:0 r/w: sector number register (map to command block 1f3h) port 6004h : bit function description default reset value : 00h 7:0 r/w: cyclinder low register (map to command block 1f4h) port 6005h : bit function description default reset value : 00h 7:0 r/w: cyclinder high register (map to command block 1f5h) port 6006h : bit function description default reset value : a0h 7:0 r/w: drive/head register (map to command block 1f6h) port 6007h : bit function description default reset value : 00h 7:0 r: command register (map to command block 1f7h) port 6008h : bit function description buffer ram size control register default reset value : 40h 7 r/w: test mode 1 for hap/dap test 0 : disable 1 : enable 6 r/w: bit write gate state of drive 0 : enable 1 : disable
14 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 bit function description 5 r: pcmcia/ata 0 : ata extension mode 1 : pcmcia mode 4 r/w: auto dap increment 0 : disable 1 : enable 3 r/w: shadow rom control 0 : disable 1 : enable 2:0 r/w: buffer ram size control 00x : 32kw 010 : 16kw 011 : 8kw 100 : 4kw 101 : 2kw 110 : 1kw 111 : 512w port 6009h : bit function description host interrupt status default reset value : 00h 7 r: power-down timer time-out detected 6 r: card configuration register write detected 5 r: cis accessed detected 4 r: hreset detected 3 r: pc srst(or pcmcia srst) detected 2 r: pc status read detected 1 r: pc selection 0 r: pc transfer done
15 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 port 600ah : bit function description host interrupt enable default reset value : 00h 7 r/w: power-down timer time-out detected enable. 6 r/w: card configuration register write detected enable 5 r/w: cis accessed detected enable 4 r/w: hreset detected enable 3 r/w: pc srst(pcmcia srst) detected enable 2 r/w: pc status read detected enable 1 r/w: pc selection enable 0 r/w: pc transfer done enable port 600bh : bit function description default reset value : 00h 7:0 r: feature register (map to command block 1f1h) port 600ch : bit function description ecc control register default reset value : 00h 7 r/w: ecc function suspend 0 : normal 1 : suspend 6 r/w: correction speed select 0 : full speed 1 : half speed 5 r/w: encode/decode function selection 0 : encode 1 : decode 4 r/w: reset ecc circuit 0 : reset 1 : normal 3 r: uncorrectable error flag 2 r: correctable error flag 1 r: correction done flag 0 r/w: start ecc correct function enable/disable 0 : disable 1 : enable
16 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 port 600dh : bit function description default reset value : 0000h 15:0 r/w : ecc 0 register port 600eh : bit function description default reset value : 0000h 15:0 r/w : ecc 1 register port 600fh : bit function description default reset value : 0000h 15:0 r/w : ecc 2 register port 6010h : bit function description default reset value : 00h 7:0 r: configuration option register (map to attribute memory 200h) port 6011h : bit function description default reset value : 00h 7:0 r: card configuration and status register (map to attribute memory 202h) port 6012h : bit function description default reset value : 0ch 7:0 r: pin replacement register (map to attribute memory 204h) port 6013h : bit function description default reset value : 00h 7:0 r: socket and copy register (map to attribute memory 206h)
17 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 port 6014h : bit function description default reset value : 0000h 15:0 r/w : host address pointer port 6015h : bit function description default reset value : 00ffh 15:0 r/w : at stop pointer port 6016h : bit function description default reset value : 0000h 15:0 r/w : disk address pointer port 6017h : bit function description dma control register default reset value : 08h 7 r/w: drive ready (drive 1) 6 r/w: drive seek complete (drive 1) 5 r/w: set bsy upon xfer done 0 : disable 1 : enable 4 r/w: enable auto interrupts - at only 0 : disable 1 : enable 3 r/w: buffer ram chip enable 0 : enable 1 : disable 2 r/w: host bus direction 0 : start buffer -> at bus 1 : start at bus -> buffer when set 1 r: a completion of at dma xfer 0 r/w: start data transfer between at bus and buffer ram 0 : disable 1 : enable
18 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 port 6018h : bit function description 15:0 r/w : access port into buffer ram port 6019h : bit function description pcmcia control register 7 r: ata extension mode 6 r: common memory mode 5 r: i/o mode 4 r/w: host ready 3 r/w: no drive address 2 r/w: internal registers write pulse width 0 : 2 system clock 1 : 1 system clock 1 r/w: force ata mode 0 r/w: force pcmcia mode port 601ah : bit function description auxi_ctl_1 reg. default reset value : 00h 7 r/w : dasp 6 r/w : host interrupt level mode or pulse mode select 0: level mode 1: pulse mode 5 r/w : pdiag 4 r/w : dasp output enable 3 r/w: write protect enable 0: disable 1: enable 2 r/w: pdiag output enable 1 r/w: master/slave mode enable 0: disable 1: enable 0 r/w: master/salve of ata mode 0: master 1: slave
19 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 port 601bh : bit function description auxi_ctl_2 reg. default reset value : 00h 7:4 reserved. 3 r/w: force the cpu that fetch codes from flash memory array 2 r/w: force the system that become ice debugging mode 1 r/w: host interface reset polarity 0: low active 1: high active 0 r/w: disk interrupt polarity 0: low active 1: high active port 601ch : bit function description auxi_ctl_3 reg. default reset value : 0000h 15 reserved 14 r/w : test mode 2 for timer 0 : normal mode 1 : test mode enable 13 r : drq 12 r : time out status 1 : time out event occurence 11 r/w: timer enable/disable 0 : disable 1 : enable
20 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 port 601ch : bit function description 10:9 r/w: pow er-down timer time-out select for 25mhz main clock 00 : 16 x 1.28 = 20.48 sec. 01 : 8 x 1.28 = 10.24 sec. 10 : 4 x 1.28 = 5.12 sec. 11 : 2 x 1.28 = 2.56 sec. 8 r : ice debugging mode detected 0 : ice debugging mode 1 : normal 7 r/w : inverted data bus for access flash memory. 0 : inverted 1 : non-inverted 6 r: external rom detect. 0: firmware stored in external rom 1: firmware stored in flash memory array 5:4 r/w: shadow rom space control 00 : 512 bytes, range: 7400h ~ 74ffh 01 : 1kbytes, range: 7400h ~ 75ffh 10 : 1.5kbytes, range: 7400h ~ 76ffh 11 : 2kbytes, range: 7400h ~ 77ffh 3:2 r : master/slave mode detect in ata mode 00 : master of two drives 10 : slave of two drives 11 : one drive 1 r/w: pio/dma mode select 0: pio mode 1: dma mode 0 r/w: led output port 601dh : bit function description default reset value : 0000h 9:0 r/w : flash memory read address fa[24:15] latch for random mode when data space 8000h ~ ffffh is read, the output of the flash memory read address latch will be used.
21 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 for sequential mode this register has different definitions 9:8 reserved 7:5 r/w: fce select for sequential mode 000: fce0 001: fce2 010: fce4 011: fce6 100: fce1 101: fce3 110: fce5 111: fce7 4 r/w: command latch enable (fa19/cle) 0 : disable 1 : enable 3 r/w: address latch enable (fa18/ale) 0 : disable 1 : enable 2:0 reserved port 601eh : bit function description flash memory control register default reset value : 08ah 7 r/w: flash memory deep power down control 0 0 : enable power down pin pwd0# active or fa23=1 for 16mbit random access flash memory 1 : disable 6 r : ready / busy status 0 : busy 1 : ready 5:4 r/w: flash memory type select 00 : 4m flash memory /bank 0 select for sequential select 01 : 16m flash memory /bank 1 select for sequential select 10 : reserved 11 : reserved
22 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 bit function description 3 r/w: flash memory deep power down control 1 0 : enable power down pin pwd1# active or fa23=0 for 16mbit random access flash memory 1 : disable 2 r/w: ce# enable for sequential mode 0 : disable 1 : enable 1 r/w: sequential mode select 0 : random mode 1 : sequential mode 0 r/w: flash memory write pulse width control 0 : 1 system clock 1 : 2 system clock port 601fh : bit function description default reset value : 0000h r/w : flash memory write address fa[24:15] latch for random mode when data space 8000h ~ ffffh is write or program space 8000h ~ ffffh is read, the output of the flash memory write address latch will be used. for sequential mode this register is reserved.
23 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 electrical specifications dc characteristics 1 : ta = 0 o c to 70 o c, vcc = 5v 10% symbol parameter min max units conditions vcc power supply voltage 4.5 5.5 v vil1 input low voltage (ttl) 0.8 v vcc=5v vih1 input high voltage (ttl) 2.0 v vcc=5v vil2 input low voltage (cmos) 0.8 v vcc=5v vih2 input high voltage (cmos) 3.5 v vcc=5v vol output low voltage 0.4 v iol=8ma voh output high voltage 2.4 v ioh=-8ma icc1 supply current 1 40 ma f = 25mhz, active mode, cl = 0pf, vcc=5.5volt, temperature= 0 o c icc2 supply current 2 35 ma f = 25mhz, idle mode, cl = 0pf, vcc=5.5volt, temperature= 0 o c icc3 supply currect 3 10 ma f = 25mhz, standby mode, cl = 0pf, vcc=5.5volt, temperature= 0 o c icc4 supply current 4 1 ma f = 0mhz, sleep mode, cl = 0pf, vcc=5.5volt, temperature= 0 o c il input leakage 10 ua 0< vin < vcc cin input capacitance 14 pf vin=0v cout output capacitance 16 pf vout=0v note : during transitions, inputs may undershoot to -2.0v for periods less than 20ns and overshoot to vcc + 2.0v for periods less than 20ns.
24 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 dc characteristics 2 : ta = 0 o c to 70 o c, vcc = 3.3v 5% symbol parameter min max units conditions vcc power supply voltage 3.1 3.5 v vil1 input low voltage(ttl) 0.8 v vcc=3.3v vih1 input high voltage(ttl) 2.0 v vcc=3.3v vil2 input low voltage(cmos) 0.8 v vcc=3.3v vih2 input high voltage(cmos) 2.7 v vcc=3.3v vol output low voltage 0.4 v iol=4ma voh output high voltage 2.2 v ioh=-4ma icc1 supply current 1 20 ma f = 16mhz, active mode, cl = 0pf, vcc=3.5volt,temperature= 0 o c icc2 supply current 2 15 ma f = 16mhz, idle mode, cl = 0pf, vcc=3.5volt,temperature= 0 o c icc3 supply currect 3 5 ma f = 16mhz, standby mode, cl = 0pf, vcc=3.5volt,temperature= 0 o c icc4 supply current 4 0.5 ma f = 0mhz, sleep mode, cl = 0pf, vcc=3.5volt,temperature= 0 o c il input leakage 10 ua 0< vin < vcc cin input capacitance 14 pf vin=0v cout output capacitance 16 pf vout=0v note : during transitions, inputs may undershoot to -2.0v for periods less than 20ns and overshoot to vcc + 2.0v for periods less than 20ns.
25 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 ac characteristics (condition : ta=0 o c to 70 o c, vcc = 5v 10% or vcc = 3.3v 5%) dsp interface timing vcc = 5v 10% symbol description min. typ. max. unit tw in ice mode, wr# pulse duration when the data are accessed 4tc by external dsp. trd in ice mode, rd# to output delay when the data are accessed 34 ns by external dsp. tcs chip select access cycle 1.5tc 4.5tc ns taa address access cycle 1.5tc 4.5tc ns trds data setup time before rd# high 12 ns tdh data hold time after rd# high 0 ns vcc = 3.3v 5% symbol description min. typ. max. unit tw in ice mode, wr# pulse duration when the data are accessed 4tc by external dsp. trd in ice mode, rd# to output delay when the data are accessed 34 ns by external dsp. tcs chip select access cycle 1.5tc 4.5tc ns taa address access cycle 1.5tc 4.5tc ns trds data setup time before rd# high 15 ns tdh data hold time after rd# high 0 ns
26 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 wr# dce# a[15:0] tdh trds tcs ta a tw rd# d[15:0] a[15:0] hd[15:0] dce#/pce# rd# dce# a[15:0] tr d d[15:0]
27 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 power reset timing vcc = 5v 10% or vcc = 3.3v 5% symbol description min. typ. max. unit tw(rst) reset low pulse width 3tc ns clock timing vcc = 5v 10% symbol description min. typ. max. unit tc(c) clock cycle time 40 ns tlpd(c) clock low pulse duration(tc=40ns) 16 24 ns thpd(c) clock high pulse duration(tc=40ns) 16 24 ns vcc = 3.3v 5% symbol description min. typ. max. unit tc(c) clock cycle time 62.5 ns tlpd(c) clock low pulse duration(tc=62.5ns) 25 37.5 ns thpd(c) clock high pulse duration(tc=62.5ns) 25 37.5 ns tw(rst) clk in pwr rst# tc tlpd thp
28 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 interrupt timing vcc = 5v 10% symbol description min. typ. max. unit tw int1# low pulse duration 1.5tc ns tf int1# fall time 10 ns vcc = 3.3v 5% symbol description min. typ. max. unit tw int1# low pulse duration 1.5tc ns tf int1# fall time ns hold# timing vcc = 5v 10% or vcc = 3.3v 5% symbol description min. typ. max. unit td(al-h) hlda# low to address tri-state 0 ns td(hh-ha) hold# high to hlda# high 0 0.5tc 0.5tc+10 ns ten(ah-a) address driven after hlda# high 0.5tc -10 0.5tc tc ns hold# int1 td(al-h) td(hh-ha) tf hlda# ad[15:0] tw ten(ah-a)
29 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 pcmcia bus timing 1: common memory and attribute memory access timing vcc = 5v 10% symbol parameter min (ns) max (ns) t1 chip enable setup time before output enable 0 t2 output data enable time from hoe# 31 t3 chip disable hold time following output disable 1.5 t4 output data disable time following hoe# 10.5 t5 chip enable setup time before hwe# 0 t6 chip disable hold time following write disable 2 t7 data setup time before hwe# 0 t8 data hold time following hwe# 2.5 vcc = 3.3v 5% symbol parameter min (ns) max (ns) t1 chip enable setup time before output enable 0 t2 output data enable time from hoe# 47 t3 chip disable hold time following output disable 3 t4 output data disable time following hoe# 17 t5 chip enable setup time before hwe# 0 t6 chip disable hold time following write disable 2.5 t7 data setup time before hwe# 0 t8 data hold time following hwe# 3
30 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 ce[2:1]# hoe# ha[10:0] reg# common memory and attribute memory read timing t2 t1 hd[15:0] t4 t3 ce[2:1]# hwe# ha[10:0] reg# common memory and attribute memory writetiming t5 hd[15:0] t7 t8 t6
31 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 pcmcia bus timing 2: i/o mode access timing vcc = 5v 10% symbol parameter min (ns) max (ns) t1 address hold time following ior# 2 t2 reg# setup time before ior# 0 t3 reg# hold time following ior# 0 t4 ce# setup time before ior# 0 t5 ce# hold time following ior# 2 t6 address setup time before ior# 0 t7 inpack delay from ior# falling 10 t8 inpack delay from ior# rising 10.5 t9 iois16 falling delay after address changed 14 t10 data delay after ior# falling 32 t11 iois16 rising delay after address changed 12.5 t12 data hold time following ior# 20 t13 address hold time following iow# 3 t14 reg# setup time before iow# 0 t15 reg# hold time following iow# 0 t16 ce# setup time before iow# 0 t17 ce# hold time following iow# 2 t18 address setup time before iow# 0 t19 iois16 rising delay after address changed 10.5 t20 iois16 falling delay after address changed 14 t21 data setup time before iow# 0 t22 data hold time following iow# 2.5
32 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 vcc = 3.3v 5% symbol parameter min (ns) max (ns) t1 address hold time following ior# 2 t2 reg# setup time before ior# 0 t3 reg# hold time following ior# 0 t4 ce# setup time before ior# 0 t5 ce# hold time following ior# 2 t6 address setup time before ior# 0 t7 inpack delay from ior# falling 18 t8 inpack delay from ior# rising 18 t9 iois16 falling delay after address changed 23.5 t10 data delay after ior# falling 47 t11 iois16 rising delay after address changed 20 t12 data hold time following ior# 31 t13 address hold time following iow# 4 t14 reg# setup time before iow# 0 t15 reg# hold time following iow# 0 t16 ce# setup time before iow# 0 t17 ce# hold time following iow# 2.5 t18 address setup time before iow# 0 t19 iois16 rising delay after address changed 20 t20 iois16 falling delay after address changed 23.5 t21 data setup time before iow# 0 t22 data hold time following iow# 3
33 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 ce[2:1]# inpack# ha[10:0] id read timing iois16# reg# ior# t6 t2 hd[15:0] t1 t4 t7 t8 t11 t12 t9 t10 t3 t5 i/o write timing ce[2:1]# ha[10:0] iois16# reg# iow# t18 t14 hd[15:0] t13 t16 t19 t22 t20 t21 t15 t17
34 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 flash memory interface timing vcc = 5v 10% symbol parameter min. max. unit tw(a-ce) fce# fall time after dsp address decode when write 5.5 15 ns twas fce# setup time before wrflash# falling edge 10 30 ns tw(wrflash) wrflash# low pulse duration 1tc* ns tr(a-ce) fce# fall time after dsp address decode when read 5.5 15 ns tr(rd-0e) rdflash# fall time after rd# falling edge 4.5 11.5 ns vcc = 3.3v 5% symbol parameter min. max. unit tw(a-ce) fce# fall time after dsp address decode when write 8 24.5 ns twas fce# setup time before wrflash# falling edge 15 50 ns tw(wrflash) wrflash# low pulse duration 1tc* ns tr(a-ce) fce# fall time after dsp address decode when read 8 25 ns tr(rd-0e) rdflash# fall time after rd# falling edge 7 20 ns * note:these timing are only for 1-system clock of flash memory write pulse is employed (601e[0]=0). if 2-system clock of pulse width is selected (601e[0]=1), the minimum of tw(wrflash) is 2tc.
35 MX9691A p/n:pm0539 rev. 1.0, oct. 02, 1998 latchup characteristics min. max. input voltage with respect to gnd on all vcc pins -2.0v 12.0v input voltage with respect to gnd on all i/o pins -2.0v vcc+2.0v current -100ma +100ma includes all pins except gnd. test conditions : vcc=5.0v, one pin at a time. wrflash# a[15:0] flash memory write timing fce[7:0] wr# tw(a-ce) tw a s tw(wrflash) rdflash# a[15:0] flash memory read timing fce[7:0] rd# tr(a-ce) tr a s
MX9691A 36 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-509-3300 fax:+886-2-509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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